SN74LV4320A Datasheet | Texas Instruments

Feature Allows Floating Input Conditions D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 250 m A Per JESD 17 D ESD - 15-k V Human-Body Model - +4-k V IEC61000-4-2, Contact Discharge (Latch-Up Immune) description /ordering information This pact Flash (CF) interface chip is designed to provide a single-chip solution for CF card interfaces. Separate VCC rails for the system bus side and the CF connector bus side allow voltage-level shifting. This is helpful for interfacing between a core chipset, which may operate from 3.3 V down to 1.65 V, and CF cards, which operate from 3.3-V or 5-V supply voltages. All the input buffers feature the input-disable function, which allows conditional floating input signals. The input, output, and I/O buffers on the CF connector side have been defined to ply with CF+ and pact Flash specification revisions 1.4 and 2.0. This device has 16-bit data lines and 24-bit address/mand lines. CD1 and CD2 have internal pullup resistors to pull them to a high logic state if there is no card in the CF slot. The presence of a CF card in the CF card slot generates a low logic signal at SCD. A separate power-supply pin, VCC_SD, controls the SCD output buffer. The SCD signal can be used to control a voltage regulator, which may power the CF slot and the CF side of this device. VCC_SD is particularly helpful when the core processor operates at a low VCC, but the regulator needs a higher control signal voltage. The MASTER_EN signal controls all the buffers and transceivers except CD1 and CD2. If MASTER_EN is high, the SN74LV4320A is in a power-down mode. The BUF_EN signal, in conjunction with MASTER_EN, controls the 11-bit address lines and 13-bit control/mand lines. The 16-bit data lines use two separate enable signals. ENL, in conjunction with MASTER_EN, controls the lower 8-bit data lines (D07- D00). ENH, in conjunction with MASTER_EN, controls the upper 8-bit data lines (D15- D08). A DIR(S/CF) input controls the data...