Datasheet4U Logo Datasheet4U.com

SN74LV573A - Octal Transparent D-Type Latches

Description

The 'LV573A devices are octal transparent D-type latches designed for 2 V to 5.5 V VCC operation.

Features

  • VCC operation of 2 V to 5.5 V.
  • Max tpd of 8 ns at 5 V.
  • Typical VOLP (Output Ground Bounce) latch-up performance exceeds 250 mA per 2.3 V at VCC = 3.3 V, TA = 25°C.
  • Support mixed-mode voltage operation on all ports.
  • Ioff supports partial-power-down mode operation.
  • Latch-up performance exceeds 250 mA per JESD 17 2.

📥 Download Datasheet

📁 Similar Datasheet

  • SN74LVC1G125 - high performance non-inverting buffer (UMW)
  • SN74LVC1G34 - Single buffer (UMW)
  • SN74L71 - AND-Gate R-S Master-Slave F-F (National Semiconductor)
  • SN74L74N - Dual D-Type Flip-Flop (ETC)
  • SN74LS00 - QUAD 2-INPUT NAND GATE (Motorola)
  • SN74LS00 - Quad 2-Input NAND Gate (ON Semiconductor)
  • SN74LS02 - QUAD 2-INPUT NOR GATE (Motorola)
  • SN74LS02 - QUAD 2-INPUT NOR GATE (ON Semiconductor)
  • SN74LS04 - Hex Inverter (ON Semiconductor)
  • SN74LS04 - HEX INVERTER (Motorola)
Other Datasheets by Texas Instruments

Full PDF Text Transcription

Click to expand full text
SN74LV573A SCLS411J – APRIL 1998 – REVISED MARCH 2023 SN74LV573A Octal Transparent D-Type Latches With 3-State Outputs 1 Features • VCC operation of 2 V to 5.5 V • Max tpd of 8 ns at 5 V • Typical VOLP (Output Ground Bounce) latch-up performance exceeds 250 mA per <0.8 V at VCC = 3.3 V , TA = 25°C • Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C • Support mixed-mode voltage operation on all ports • Ioff supports partial-power-down mode operation • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Buffer Registers • Bidirectional Bus Drivers • Working Registers To seven other channels 3 Description The 'LV573A devices are octal transparent D-type latches designed for 2 V to 5.5 V VCC operation.
Published: |