SN74LV86A-EP Datasheet | Texas Instruments

SN74LV86AĆEP QUADRUPLE 2ĆINPUT EXCLUSIVEĆOR GATE D Controlled Baseline - One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of - 40°C to 105°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D 2-V to 5.5-V VCC Operation † ponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold pound life. Such qualification testing should not be viewed as justifying use of this ponent beyond specified performance and environmental limits. SCLS567A - JANUARY 2004 - REVISED MAY 2004 D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C D Supports Mixed-Mode Voltage Operation on All Ports PW PACKAGE (TOP VIEW) 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y description/ordering information The SN74LV86A is a quadruple 2-input exclusive-OR gate designed for 2-V to 5.5-V VCC operation. This device contains four independent 2-input exclusive-OR gates. It performs the Boolean function Y = A ę B or Y = AB + AB in positive logic. A mon application is as a true/plement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. ORDERING INFORMATION PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING - 40°C to 105°C TSSOP - PW Tape and reel SN74LV86ATPWREP LV86AEP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at .ti./sc/package. FUNCTION TABLE (each...