Datasheet4U Logo Datasheet4U.com

SN74LVC1G79 - Single Positive-Edge-Triggered D-Type Flip-Flop

Description

The SN74LVC1G79 device is a single positive-edgetriggered D-type flip-flop that is designed for 1.65-V to 5.5-V VCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse.

Features

  • 1 Available in the Texas Instruments NanoFree™ Package.
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II.
  • ESD Protection Exceeds JESD 22.
  • 2000-V Human-Body Model (A114-A).
  • 200-V Machine Model (A115-A).
  • 1000-V Charged-Device Model (C101).
  • Supports 5-V VCC Operation.
  • Inputs Accept Voltages to 5.5 V.
  • Supports Down Translation to VCC.
  • Max tpd of 6 ns at 3.3 V and 50 pF load.
  • Low Power Consumpt.

📥 Download Datasheet

Datasheet preview – SN74LVC1G79

Datasheet Details

Part number SN74LVC1G79
Manufacturer Texas Instruments
File Size 1.47 MB
Description Single Positive-Edge-Triggered D-Type Flip-Flop
Datasheet download datasheet SN74LVC1G79 Datasheet
Additional preview pages of the SN74LVC1G79 datasheet.

📁 Similar Datasheet

  • SN74LVC1G125 - high performance non-inverting buffer (UMW)
  • SN74LVC1G34 - Single buffer (UMW)
  • SN74L71 - AND-Gate R-S Master-Slave F-F (National Semiconductor)
  • SN74L74N - Dual D-Type Flip-Flop (ETC)
  • SN74LS00 - QUAD 2-INPUT NAND GATE (Motorola)
  • SN74LS00 - Quad 2-Input NAND Gate (ON Semiconductor)
  • SN74LS02 - QUAD 2-INPUT NOR GATE (Motorola)
  • SN74LS02 - QUAD 2-INPUT NOR GATE (ON Semiconductor)
  • SN74LS04 - Hex Inverter (ON Semiconductor)
  • SN74LS04 - HEX INVERTER (Motorola)
Other Datasheets by Texas Instruments

Full PDF Text Transcription

Click to expand full text
Product Folder Order Now Technical Documents Tools & Software Support & Community SN74LVC1G79 SCES220U – APRIL 1999 – REVISED APRIL 2017 SN74LVC1G79 Single Positive-Edge-Triggered D-Type Flip-Flop 1 Features •1 Available in the Texas Instruments NanoFree™ Package • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 6 ns at 3.3 V and 50 pF load • Low Power Consumption, 10-µA Max ICC • ±24-mA Output Drive at 3.
Published: |