SN74LVC1G79 Datasheet | Texas Instruments

Features - 1 Available in the Texas Instruments Nano Free™ Package - Latch-Up Performance Exceeds 100 m A Per JESD 78, Class II - ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) - Supports 5-V VCC Operation - Inputs Accept Voltages to 5.5 V - Supports Down Translation to VCC - Max tpd of 6 ns at 3.3 V and 50 p F load - Low Power Consumption, 10-µA Max ICC - ±24-m A Output Drive at 3.3 V - Ioff supports Partial-Power-Down Mode and Back- Drive Protection 2 Applications - Test and Measurement - Enterprise Switching - Tele Infrastructure - Personal Electronics - White Goods 3 Description The SN74LVC1G79 device is a single positive-edgetriggered D-type flip-flop that is designed for 1.65-V to 5.5-V VCC operation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output. Nano Free™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. Device Information(1) PART NUMBER PACKAGE BODY SIZE SN74LVC1G79DBV SOT-23 (5) 2.90 mm × 1.60 mm SN74LVC1G79DCK SC70 (5) 2.00 mm × 1.25 mm SN74LVC1G79DRL SOT (5) 1.60 mm × 1.20 mm SN74LVC1G79YZP DSBGA (5) 1.14 mm × 0.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive...