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SN74LVC2G79 - Dual Positive-Edge-Triggered D-Type Flip-Flop

Description

This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse.

Features

  • 1.
  • 2 Available in the Texas Instruments NanoFree™ Package.
  • Supports 5-V VCC Operation.
  • Inputs Accept Voltages to 5.5 V.
  • Max tpd of 4.2 ns at 3.3 V.
  • Low Power Consumption, 10-μA Max ICC.
  • ±24-mA Output Drive at 3.3 V.
  • Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C.
  • Ioff Feature Supports Live Insertion, PartialPower-Down Mode Oper.

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Full PDF Text Transcription

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SN74LVC2G79 www.ti.com SCES498E – OCTOBER 2003 – REVISED DECEMBER 2013 Dual Positive-Edge-Triggered D-Type Flip-Flop Check for Samples: SN74LVC2G79 FEATURES 1 •2 Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Max tpd of 4.2 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.
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