SN74LVT125-EP Datasheet | Texas Instruments

FEATURES - Controlled Baseline - One Assembly/Test Site, One Fabrication Site - Extended Temperature Performance of - 40°C to 125°C - Enhanced Diminishing Manufacturing Sources (DMS) Support - Enhanced Product-Change Notification - Qualification Pedigree(1) - ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p F, R = 0) - Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) (1) ponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold pound life. Such qualification testing should not be viewed as justifying use of this ponent beyond specified performance and environmental limits. SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS SCBS796A - JANUARY 2004 - REVISED JUNE 2005 - Supports Unregulated Battery Operation Down to 2.7 V - Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Partial-Power-Down Mode Operation - Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors D OR PW PACKAGE (TOP VIEW) 1OE 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND 7 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y DESCRIPTION /ORDERING INFORMATION This bus buffer is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE) input is high. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not remended. This device is fully specified for partial-power-down applications...