Datasheet4U Logo Datasheet4U.com

SN74LVT125 - 3.3-V ABT QUADRUPLE BUS BUFFERS

General Description

This bus buffer is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

Key Features

  • independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE) input is high. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
SN74LVC1G125 high performance non-inverting buffer UMW
SN74LVC1G34 Single buffer UMW
SN74L71 AND-Gate R-S Master-Slave F-F National Semiconductor
SN74L74N Dual D-Type Flip-Flop ETC
SN74LS00 QUAD 2-INPUT NAND GATE Motorola

Other Datasheets by Texas Instruments

Part Number Description
SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFERS
SN74LVT125-Q1 3.3-V ABT QUADRUPLE BUS BUFFERS
SN74LVT162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS
SN74LVT162244A 3.3-V ABT 16-BIT BUFFERS/DRIVERS
SN74LVT162245A 3.3-V ABT 16-BIT BUS TRANSCEIVERS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
D Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) D Supports Unregulated Battery Operation Down to 2.7 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Ioff Supports Partial-Power-Down Mode Operation D Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) SN74LVT125 3.