SN74LVTH125-EP Datasheet | Texas Instruments

D Controlled Baseline - One Assembly/Test Site, One Fabrication Site D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) D Supports Unregulated Battery Operation Down to 2.7 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C † ponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold pound life. Such qualification testing should not be viewed as justifying use of this ponent beyond specified performance and environmental limits. SN74LVTH125ĆEP 3.3ĆV ABT QUADRUPLE BUS BUFFER WITH 3ĆSTATE OUTPUTS SCBS765 - NOVEMBER 2003 D Ioff and Power-Up 3-State Support Hot Insertion D Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors D Latch-Up Performance Exceeds 500 m A Per JESD 17 D ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) PW PACKAGE (TOP VIEW) 1OE 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND 7 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y description/ordering information This bus buffer is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVTH125 Features independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE) input is...