SN74SSTV32852-EP Description
/ORDERING INFORMATION This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II patible.
SN74SSTV32852-EP Key Features
- 2 Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of -40°C to 85°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree (1)
- Member of the Texas Instruments Widebus™ Family
- 1-to-2 Outputs Support Stacked DDR DIMMs
- Supports SSTL_2 Data Inputs
- Outputs Meet SSTL_2 Class II Specifications