SN75ALS164 Datasheet | Texas Instruments

description SLLS022C - JUNE 1986 - REVISED MAY 1998 DW PACKAGE (TOP VIEW) GPIB I/O Ports SC 1 TE 2 REN 3 IFC 4 NDAC 5 NRFD 6 DAV 7 EOI 8 ATN 9 SRQ 10 NC 11 GND 12 24 VCC 23 ATN + EOI 22 REN 21 IFC 20 NDAC 19 NRFD 18 DAV Terminal I/O Ports 17 EOI 16 ATN 15 SRQ 14 NC 13 DC - No internal connection NOT REMENDED FOR NEW DESIGNS The SN75ALS164 eight-channel general-purpose interface bus transceiver is a monolithic, high-speed, advanced low-power Schottky device designed to meet the requirements of IEEE Standard 488-1978. Each transceiver is designed to provide the bus-management and data-transfer signals between operating units of a multiple-controller instrumentation system. When bined with the SN75ALS160 octal bus transceiver, the SN75ALS164 provides the plete 16-wire interface for the IEEE 488 bus. The SN75ALS164 features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. All outputs are disabled (at the high-impedance state) during VCC power-up and power-down transitions for glitch-free operation. The direction of data flow through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SN75ALS164 is identical to the SN75ALS162 with the addition of an OR gate to help simplify board layouts in several popular applications. The ATN and EOI signals are ORed to provide the ATN + EOI output, which is a standard totem-pole output. The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when supply voltage VCC is 0. The drivers are designed to handle loads up to 48 m A of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 m V minimum for increased noise immunity. All receivers have 3-state outputs that present a high impedance to the terminal when disabled. The SN75ALS164 is characterized for operation from 0°C...