SN75LVDS388 Datasheet | Texas Instruments

SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS D Eight Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard D Integrated 110-Ω Line Termination Resistors on LVDT Products D Designed for Signaling Rates† Up To 630 Mbps D SN65 Version’s Bus-Terminal ESD Exceeds 15 k V D Operates From a Single 3.3-V Supply D Propagation Delay Time of 2.6 ns (Typ) D Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns D LVTTL Levels Are 5-V Tolerant D Open-Circuit Fail Safe D Flow-Through Pin Out D Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch description The ‘LVDS388 and ‘LVDT388 (T designates integrated termination) are eight differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight differential receivers will provide a valid logical output state with a +100-m V differential input voltage within the input mon-mode voltage range. The input mon-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals always require the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT product eliminates this external resistor by integrating it with the receiver. SLLS448A - SEPTEMBER 2000 - REVISED MAY 2001 NOT REMENDED FOR NEW DESIGNS For Replacement Use ’LVDx388A ’LVDS388, ’LVDT388 DBT PACKAGE (TOP VIEW) A1A 1 A1B 2 A2A 3 A2B 4 NC 5 B1A 6 B1B 7 B2A 8 B2B 9 NC 10 C1A 11 C1B 12 C2A 13 C2B 14 NC 15 D1A 16 D1B 17 D2A 18 D2B 19 38 GND 37 VCC 36 ENA 35 A1Y 34 A2Y 33 ENB 32 B1Y 31 B2Y 30 GND 29 VCC 28 GND 27 C1Y 26 C2Y 25 ENC 24 D1Y 23 D2Y 22 END 21 VCC 20 GND logic...