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SNJ54HC42J - 4-LINE TO 10-LINE DECODERS

General Description

These decimal decoders consist of eight inverters and ten 4-input NAND gates.

The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates.

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Full PDF Text Transcription for SNJ54HC42J (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for SNJ54HC42J. For precise diagrams, and layout, please refer to the original PDF.

D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 14 ns D ±4-mA Output Drive at...

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nsumption, 80-µA Max ICC D Typical tpd = 14 ns D ±4-mA Output Drive at 5 V SN54HC42 . . . J OR W PACKAGE SN74HC42 . . . D, N, OR NS PACKAGE (TOP VIEW) 01 12 23 34 45 56 67 GND 8 16 VCC 15 A 14 B 13 C 12 D 11 9 10 8 97 6 7 SN54HC42, SN74HC42 4ĆLINE TO 10ĆLINE DECODERS (1 of 10) SCLS091D − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Low Input Current of 1 µA Max D Full Decoding of Input Logic D All Outputs Are High for Invalid BCD Conditions D Also for Applications as 3-Line to 8-Line Decoders SN54HC42 . . .

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