TFP401A-EP Datasheet | Texas Instruments

.ti. SLDS160A - MARCH 2009 - REVISED JULY 2011 TI Panel Bus™ DIGITAL RECEIVER Check for Samples: TFP401A-EP Features - 2 Supports Pixel Rates Up to 165 MHz (including 1080p and WUXGA at 60Hz) - Digital Visual Interface (DVI) Specification pliant (1) - True-Color, 24 Bit/Pixel, 16.7M Colors at One or Two Pixels Per Clock - Laser Trimmed Internal Termination Resistors for Optimum Fixed Impedance Matching - Skew Tolerant Up to One Pixel Clock Cycle - 4x Over-Sampling - Reduced Power Consumption - 1.8 V Core Operation With 3.3 V I/Os and Supplies (2) - Reduced Ground Bounce Using Time-Staggered Pixel Outputs - Low Noise and Power Dissipation Using TI Power PAD™ Packaging - Advanced Technology Using TI 0.18-mm EPIC-5™ CMOS Process - TFP401A Incorporates HSYNC Jitter Immunity (3) (1) The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays. The TFP401A is pliant to the DVI Specification Rev. 1.0. (2) The TFP401A has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V supplies. (3) The TFP401A incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on the transmitted HSYNC signal. SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS - Controlled Baseline - One Assembly/Test...