TI380C30A Datasheet | Texas Instruments

INTEGRATED TOKEN-RING MPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 - MARCH 1998 D Single-Chip Token-Ring Solution D IBM™ Token-Ring Network™ patible D patible With ISO/IEC IEEE Std 802.5:1992 Token-Ring Access-Method and Physical-Layer Specifications D patible With TI380FPA Packet Blaster™ D Glueless Memory Interface D Digital Phase-Locked Loop (PLL) - Precise Control of Bandwidths - Improved Jitter Tolerance - Minimizes Accumulated Phase Slope D Phantom Drive for Physical Insertion Onto Ring D Differential Line Receiver With Level-Dependent Frequency Equalization D Low-Impedance Differential Line Driver to Ease Transmit-Filter Design D On-Chip Watchdog Timer D Internal Crystal Oscillator for Reference-Clock Generation D Expandable LAN-Subsystem Memory up to 2M Bytes D 32-Bit Host Address Bus D 80x8x or 68xxx-Type Bus and Memory Organization D Dual-Port Direct Memory Access (DMA) and Direct Input/Output Transfers to Host Bus D Supports 8- or 16-Bit Pseudo-Direct Memory Access (PDMA) Operation D Electrostatic Discharge (ESD) Protection Exceeds 2 k V (All Pins) D 0.8-µm CMOS Technology D Token-Ring Features - 16- or 4-Megabit-Per-Second (Mbit/s) Data Rates - Supports up to 18K-Byte Frame Size (16 Mbit/s...