TI380C30A Description
TI380C30A INTEGRATED TOKEN-RING MPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 MARCH 1998 D Single-Chip Token-Ring Solution D IBM™ Token-Ring Network™ patible D patible With ISO/IEC IEEE Std 802.5:1992 Token-Ring Access-Method and Physical-Layer.
TI380C30A Key Features
- 16- or 4-Megabit-Per-Second (Mbit/s) Data Rates
- Supports up to 18K-Byte Frame Size (16 Mbit/s Only)
- Supports Universal and Local Addressing
- Early Token-Release Option (16 Mbit/s Only)
- Built-In Real-Time Error Detection
- Automatic Frame-Buffer Management
- 2-MHz to 33-MHz System-Bus Clock
- Slow-Clock Low-Power Mode