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TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
D Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1 to (216 −1) and Generates an Internal 16 × Clock
N PACKAGE (TOP VIEW)
D0 1 D1 2
40 VCC 39 RI
D Full Double Buffering Eliminates the Need
for Precise Synchronization
D Standard Asynchronous Communication
D2 3 D3 4 D4 5 D5 6
38 DCD 37 DSR 36 CTS 35 MR
Bits (Start, Stop, and Parity) Added or Deleted to or From the Serial Data Stream
D6 7 D7 8
34 OUT1 33 DTR
D Independent Receiver Clock Input D Transmit, Receive, Line Status, and Data
RCLK 9 SIN 10
SOUT 11
32 RTS 31 OUT2 30 INTRPT
Set Interrupts Independently Controlled
CS0 12 29 NC
D Fully Programmable Serial Interface
Characteristics: − 5-, 6 -, 7 -, or