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TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS
D Based Upon the T320C2xLP Core CPU
D 16-Bit Fixed-Point DSP Architecture
– Six Internal Buses for Increased
Parallelism and Performance
– 32-Bit ALU/Accumulator
– 16 × 16-Bit Single-Cycle Multiplier With a
32-Bit Product
– Block Moves for Data, Program,
I/O Space
– Hardware Repeat Instruction
D Instruction Cycle Time
’C203
’LC203
’C209
50 ns @ 5 V 50 ns @ 3.
TMS320C203 Datasheet
