TMS320C6421 Datasheet | Texas Instruments

Features - High-Performance Digital Signal Processor (C6421) - 2.5-, 2.-, 1.67-,1.43- ns Instruction Cycle Time - 400-, 500-, 600-, 700-MHz C64x+™ Clock Rate - Eight 32-Bit C64x+ Instructions/Cycle - 3200, 4000, 4800, 5600 MIPS - Fully Software-patible With C64x - mercial and Automotive (Q or S suffix) Grades - Low-Power Device (L suffix) - Veloci TI.2™ Extensions to Veloci TI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core - Eight Highly Independent Functional Units With Veloci TI.2 Extensions: - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle - Load-Store Architecture With Non-Aligned Support - 64 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional - Additional C64x+™ Enhancements - Protected Mode Operation - Exceptions Support for Error Detection and Program Redirection - Hardware Support for Modulo Loop Auto-Focus Module Operation - C64x+ Instruction Set Features - Byte-Addressable (8-/16-/32-/64-Bit Data) - 8-Bit Overflow Protection - Bit-Field Extract, Set, Clear - Normalization, Saturation, Bit-Counting - Veloci TI.2 Increased Orthogonality - C64x+ Extensions - pact 16-bit Instructions - Additional Instructions to Support plex Multiplies - C64x+ L1/L2 Memory Architecture - 128K-Bit (16K-Byte) L1P Program RAM/Cache [Flexible Allocation] - 384K-Bit (48K-Byte) L1D Data RAM/Cache [Flexible Allocation] - 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation] - Endianess: Supports Both Little Endian and Big Endian - External Memory Interfaces (EMIFs) - 16-Bit DDR2 SDRAM Memory Controller With 128M-Byte Address Space (1.8-V I/O) - Supports up to 266-MHz (data rate) bus and interfaces to DDR2-400 SDRAM - Asynchronous 8-Bit-Wide EMIF (EMIFA) With up to 64M-Byte Address Reach - Flash...