TMS320C6457 Overview
.12 1.3 Functional Block Diagram.
TMS320C6457 Key Features
- Corrected CORECLK(P|N) and ALTCORECLK max frequency, minimum period time, duty cycle, and transition times
- Corrected Period Jitter tolerance, duty cycle, and transition times for DDRREFCLK(P|N) and ALTDDRCLK
- Corrected PLL2 block diagram to include correct reference to PLLV2 voltage net
- Added DDR2CLKOUT0(N|P) and DDR2CLKOUT0(N|P) min and max frequency to PLL2 Clock Frequency Ranges table
- Removed PLLOUT term from the PLL2 Clock Frequency ranges table
- Clarified wording in the introduction of the PLL2 section and on the effective x5 multiplier that generates
- Added Table 7-4 Power Supply to Peripheral I/O Mapping to clarify the exact I/O and reference clock buffers each power
- Added Overshoot/Undershoot definition to Table 6-1