TMS320C6457
TMS320C6457 is Communications Infrastructure Digital Signal Processor manufactured by Texas Instruments.
Features bullet list.
- Corrected CORECLK(P|N) and ALTCORECLK max frequency, minimum period time, duty cycle, and transition times
- Corrected Period Jitter tolerance, duty cycle, and transition times for DDRREFCLK(P|N) and ALTDDRCLK
- Corrected PLL2 block diagram to include correct reference to PLLV2 voltage net
- Added DDR2CLKOUT0(N|P) and DDR2CLKOUT0(N|P) min and max frequency to PLL2 Clock Frequency Ranges table
- Removed PLLOUT term from the PLL2 Clock Frequency ranges table
- Clarified wording in the introduction of the PLL2 section and on the effective x5 multiplier that generates
DDR2CLKOUT0(N|P) and DDR2CLKOUT0(N|P) from DDRREFCLK(P|N) or ALTDDRCLK
- Added Table 7-4 Power Supply to Peripheral I/O Mapping to clarify the exact I/O and reference clock buffers each power supply provides power for
- Added Overshoot/Undershoot definition to Table 6-1 Absolute Maximum Ratings
- Fixed typo in Table 2-1 under the 1.2 GHz space, “1.2 V, 1.8 V, and 3.3 V” now correctly reads “1.1 V, 1.8 V, and 3.3 V”
- Fixed typo for the Mc BSP timing parameters. “P = 1/CORECLK” now correctly reads “P = 1/SYSREFCLK”
- Fixed typo in 7.3.1 Power-Supply Sequencing
- The SPRAAG5 reference now correctly references SPRAAV7
- Initial version
2 Release History
2009 Texas Instruments Incorporated
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Contents
TMS320C6457 munications Infrastructure Digital Signal Processor
SPRS582B- July 2010
1 TMS320C6457 Features
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- .11 1.1 TMS320C6457CMH/GMH BGA Package (Bottom View)
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- . . . .12 1.2...
