TMS320DM6467
Overview
- High-Performance Digital Media SoC
- C64x+ L1/L2 Memory Architecture - 594-, 729-MHz C64x+™ Clock Rate - 32K-Byte L1P Program RAM/Cache (Direct - 297-, 364.5-MHz ARM926EJ-S™ Clock Rate Mapped) - Eight 32-Bit C64x+ Instructions/Cycle - 4752, 5832 C64x+ MIPS - Fully Software-Compatible With C64x/ARM9™ - Supports SmartReflex™ [-594 only]
- Class 0
- 1.05-V and 1.2-V Adaptive Core Voltage - Extended Temp Available [-594 only] - Industrial Temp Available [-729 only]
- Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core - Eight Highly Independent Functional Units
- Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
- Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock - 32K-Byte L1D Data RAM/Cache (2-Way SetAssociative) - 128K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
- ARM926EJ-S Core - Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets - DSP Instruction Extensions and Single Cycle MAC - ARM® Jazelle® Technology - EmbeddedICE-RT™ Logic for Real-Time Debug
- ARM9 Memory Architecture - 16K-Byte Instruction Cache - 8K-Byte Data Cache - 32K-Byte RAM - 8K-Byte ROM Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
- Embedded Trace Buffer™ (ETB11™) With 4KB Results) per Clock Cycle Memory for ARM9 Debug - Load-Store Architecture With Non-Aligned
