TPS3840-Q1 Datasheet | Texas Instruments

Features 2 Applications - 1 Qualified for automotive applications - AEC-Q100 qualified with the following results: - Device temperature grade 1: - 40°C to +125°C ambient operating temperature - Device HBM ESD classification level 2 - Device CDM ESD classification level C7B - Wide operating voltage : 1.5 V to 10 V - Use external resistors to extend Vin range - Nano supply current : 350 n A (Typ), 700 n A (Max) - Fixed threshold voltage (VIT-) - Threshold from 1.6 V to 4.9 V in 0.1-V steps - High accuracy: 1% (Typ), 1.5% (Max) - Built-in hysteresis (VIT+) - 1.6 V < VIT- ≤ 3.0 V = 100 m V (typical) - 3.1 V ≤ VIT- < 4.9 V = 200 m V (typical) - Fast start-up delay (t STRT): 350 µs (Max) - Programmable capacitor-based reset time delay: - t D: 50 µs (no capacitor) to 6.2 s (10-µF) - Active-low manual reset (MR) - Three output topologies: - TPS3840DL-Q1: open-drain, active-low (RESET) - TPS3840PL-Q1: push-pull, active-low (RESET) - TPS3840PH-Q1: push-pull, active-high (RESET) - Package: 5-pin SOT-23 (DBV) - Automotive head unit and cluster - Automotive display, integrated cockpit and driver monitoring - Telematics control unit and emergency call 3 Description The TPS3840-Q1 family of voltage supervisors or reset ICs can operate at high voltage levels while maintaining very low quiescent current across the whole VDD and temperature range. TPS3840-Q1 offers best bination of low power consumption, high accuracy and low propagation delay (tp_HL= 30 µs typical). Reset output signal is asserted when the voltage at VDD drops below the negative voltage threshold (VIT-) or when manual reset is pulled to a low logic (VMR_L). Reset signal is cleared when VDD rise above VIT- plus hysteresis (VIT+) and manual reset (MR) is floating or above VMR_H and the reset time delay (t D) expires. Reset time delay can be programmed by connecting a capacitor between CT pin and ground. For a fast reset CT pin can be left floating. Additional features : Low power-on reset voltage (VPOR), built-in glitch...