KH25L2005 Datasheet | Macronix

2M-BIT [x 1] CMOS SERIAL FLASH Features GENERAL - Serial Peripheral Interface (SPI) patible -- Mode 0 and Mode 3 - 2,097,152 x 1 bit structure - 64 Equal Sectors with 4K byte each - Any Sector can be erased individually - 4 Equal Blocks with 64K byte each - Any Block can be erased individually - Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations - Latch-up protected to 100m A from -1V to Vcc +1V - Low Vcc write inhibit is from 1.5V to 2.5V PERFORMANCE - High Performance - Fast access time: 66MHz serial clock (30p F + 1TTL Load) - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-byte per block) - Low Power Consumption - Low active read current: 8m A(max.) at 66MHz and 4m A(max.) at 25MHz - Low active programming current: 15m A (max.) - Low active erase current: 15m A (max.) - Low standby current: 10u A (max.) - Deep power-down mode 1u A (typical) - Minimum 100,000 erase/program cycles SOFTWARE Features - Input Data Format - 1-byte mand code - Block Lock protection - The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase...