74AHC157 Datasheet | Nexperia

description The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin patible with Low Power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two sources under the control of a mon data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four mon output buses is a mon use of the 74AHC/AHCT157. The state of the mon data select input (S) determines the particular register from which the data es. It can also be used as function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable mon. The 74AHC/AHCT157 is logic implementation of a 4-pole, 2-position switch, where the position of the switch is determine by the logic levels applied to S. The logic equations are: - 1Y = E × (1I1 × S + 1I0 × S) - 2Y = E × (2I1 × S + 2I0 × S) - 3Y = E × (3I1 × S + 3I0 × S) - 4Y = E × (4I1 × S + 4I0 × S) 2. Features - Balanced propagation delays - All inputs have a Schmitt-trigger action - Inputs accepts voltages higher than VCC - Multiple input enable for easy expansion - Ideal for memory chip select decoding - For 74AHC157 only: operates with CMOS input levels - For 74AHCT157 only: operates with TTL input levels - ESD protection: - HBM JESD22-A114E exceeds 2000 V - MM JESD22-A115-A exceeds 200 V - CDM JESD22-C101C exceeds 1000 V - Multiple package options - Specified from -40 °C to +85 °C and from -40 °C to +125 °C Nexperia 74AHC157; 74AHCT157 Quad 2-input multiplexer 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AHC157D -40 °C to +125 °C 74AHCT157D 74AHC157PW -40 °C to +125 °C 74AHCT157PW 74AHC157BQ -40 °C to +125 °C 74AHCT157BQ Name SO16 Description...