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74AHC157 - Quad 2-input multiplexer

Description

The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard no.

7A.

Features

  • Balanced propagation delays.
  • All inputs have a Schmitt-trigger action.
  • Inputs accepts voltages higher than VCC.
  • Multiple input enable for easy expansion.
  • Ideal for memory chip select decoding.
  • For 74AHC157 only: operates with CMOS input levels.
  • For 74AHCT157 only: operates with TTL input levels.
  • ESD protection:.
  • HBM JESD22-A114E exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101C exc.

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Datasheet preview – 74AHC157

Datasheet Details

Part number 74AHC157
Manufacturer nexperia
File Size 260.18 KB
Description Quad 2-input multiplexer
Datasheet download datasheet 74AHC157 Datasheet
Additional preview pages of the 74AHC157 datasheet.

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Full PDF Text Transcription

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74AHC157; 74AHCT157 Quad 2-input multiplexer Rev. 3 — 10 September 2020 Product data sheet 1. General description The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74AHC/AHCT157. The state of the common data select input (S) determines the particular register from which the data comes.
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