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74AHC157 - Quad 2-input multiplexer

General Description

The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard No.

7A.

Key Features

  • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V.
  • Balanced propagation delays.
  • All inputs have Schmitt-trigger actions.
  • Multiple input enable for easy expansion.
  • Ideal for memory chip select decoding.
  • Inputs accept voltages higher than VCC.
  • For AHC only: operates with CMOS input levels.
  • For AHCT only: operates with TTL input levels.
  • Specified.

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Full PDF Text Transcription for 74AHC157 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for 74AHC157. For precise diagrams, tables, and layout, please refer to the original PDF.

INTEGRATED CIRCUITS DATA SHEET 74AHC157; 74AHCT157 Quad 2-input multiplexer Product specification File under Integrated Circuits, IC06 1999 Sep 24 Philips Semiconductors P...

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e under Integrated Circuits, IC06 1999 Sep 24 Philips Semiconductors Product specification Quad 2-input multiplexer FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 and +125 °C. FUNCTION TABLE See note 1. INPUT E H L L L L Not