74AHC157 Datasheet | NXP Semiconductors

FEATURES - ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V - Balanced propagation delays - All inputs have Schmitt-trigger actions - Multiple input enable for easy expansion - Ideal for memory chip select decoding - Inputs accept voltages higher than VCC - For AHC only: operates with CMOS input levels - For AHCT only: operates with TTL input levels - Specified from - 40 to +85 and +125 °C. FUNCTION TABLE See note 1. INPUT E H L L L L Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care. ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC157D 74AHC157PW 74AHCT157D 74AHCT157PW PACKAGES NORTH AMERICA PINS 74AHC157D 74AHC157PW DH 74AHCT157D 74AHCT157PW DH 16 16 16 16 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic S X L L H H n I0 X L H X X n I1 X X X L H OUTPUT n Y L L H L H DESCRIPTION 74AHC157; 74AHCT157 The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard No. 7A. The 74AHC/AHCT157 are quad 2-input multiplexers which select 4 bits of data from two sources under the control of a mon data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four mon output buses is a mon use of the ‘157’. The state of the mon data select input (S) determines the particular register from which the data es. It can also be used as a function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable mon. The ‘157’ is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determine by the logic levels applied to S. The logic equations are: 1Y = E × (1I1 × S + 1I0 × S); 2Y = E × (2I1 × S + 2I0...