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74AHC157D - Quad 2-input multiplexer

Download the 74AHC157D datasheet PDF. This datasheet also covers the 74AHC157 variant, as both devices belong to the same quad 2-input multiplexer family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard no.

7A.

Key Features

  • Balanced propagation delays.
  • All inputs have a Schmitt-trigger action.
  • Inputs accepts voltages higher than VCC.
  • Multiple input enable for easy expansion.
  • Ideal for memory chip select decoding.
  • For 74AHC157 only: operates with CMOS input levels.
  • For 74AHCT157 only: operates with TTL input levels.
  • ESD protection:.
  • HBM JESD22-A114E exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101C exc.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC157-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74AHC157D
Manufacturer Nexperia
File Size 260.18 KB
Description Quad 2-input multiplexer
Datasheet download datasheet 74AHC157D Datasheet

Full PDF Text Transcription for 74AHC157D (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for 74AHC157D. For precise diagrams, and layout, please refer to the original PDF.

74AHC157; 74AHCT157 Quad 2-input multiplexer Rev. 3 — 10 September 2020 Product data sheet 1. General description The 74AHC/AHCT157 are high-speed Si-gate CMOS devices an...

View more extracted text
l description The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74AHC/AHCT157. The state of the common data select input (S)