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74AHC574D - Octal D-type flip-flop

Download the 74AHC574D datasheet PDF. This datasheet also covers the 74AHC574 variant, as both devices belong to the same octal d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard no.

7A.

Key Features

  • I Balanced propagation delays I All inputs have a Schmitt-trigger action I 3-state non-inverting outputs for bus orientated.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC574-nexperia.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 02 — 24 January 2008 Product data sheet 1. General description The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC574; 74AHCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW the contents of the 8 flip-flops are available at the outputs.