Datasheet Details
| Part number | 74AHC74PW |
|---|---|
| Manufacturer | Nexperia |
| File Size | 251.31 KB |
| Description | Dual D-type flip-flop |
| Datasheet | 74AHC74PW 74AHC74 Datasheet (PDF) |
|
|
Overview: 74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 8 — 22 April 2020 Product data sheet 1.
This datasheet includes multiple variants, all published together in a single manufacturer document.
| Part number | 74AHC74PW |
|---|---|
| Manufacturer | Nexperia |
| File Size | 251.31 KB |
| Description | Dual D-type flip-flop |
| Datasheet | 74AHC74PW 74AHC74 Datasheet (PDF) |
|
|
|
The 74AHC74;
74AHCT74 is a high-speed Si-gate CMOS device and is pin patible with Low-Power Schottky TTL (LSTTL).
It is specified in pliance with JEDEC standard No.
| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
 |
74AHC74 | Dual D-type flip-flop | NXP |
| Part Number | Description |
|---|---|
| 74AHC74 | Dual D-type flip-flop |
| 74AHC74-Q100 | Dual D-type flip-flop |
| 74AHC74BQ | Dual D-type flip-flop |
| 74AHC74D | Dual D-type flip-flop |
| 74AHC00 | Quad 2-input NAND gate |
| 74AHC00-Q100 | Quad 2-input NAND gate |
| 74AHC00BQ | Quad 2-input NAND gate |
| 74AHC00D | Quad 2-input NAND gate |
| 74AHC02 | Quad 2-input NOR gate |
| 74AHC02-Q100 | Quad 2-input NOR gate |