74AHCT138PW Description
74AHCT138 are high-speed Si-gate CMOS devices and are pin patible with Low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard No. 74AHCT138 is a 3-to-8 line decoder/demultiplexer.
74AHCT138PW Key Features
- Balanced propagation delays
- All inputs have Schmitt-trigger action
- Demultiplexing capability
- Multiple input enable for easy expansion
- Ideal for memory chip select decoding
- Inputs accepts voltages higher than VCC
- For 74AHC138 only: operates with CMOS input levels
- For 74AHCT138 only: operates with TTL input levels
- ESD protection
- HBM JESD22-A114E exceeds 2000 V