74AHCT157-Q100 Datasheet | Nexperia

74AHC157-Q100; Quad 2-input multiplexer Rev. 2 - 10 September 2020 Product data sheet 1. General description The 74AHC/AHCT157-Q100 are high-speed Si-gate CMOS devices and are pin patible with Low Power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74AHC/AHCT157-Q100 are quad 2-input multiplexer which select 4 bits of data from two sources under the control of a mon data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four mon output buses is a mon use of the...