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74AHCT157PW - Quad 2-input multiplexer

Download the 74AHCT157PW datasheet PDF. This datasheet also covers the 74AHC157 variant, as both devices belong to the same quad 2-input multiplexer family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard no.

7A.

Key Features

  • Balanced propagation delays.
  • All inputs have a Schmitt-trigger action.
  • Inputs accepts voltages higher than VCC.
  • Multiple input enable for easy expansion.
  • Ideal for memory chip select decoding.
  • For 74AHC157 only: operates with CMOS input levels.
  • For 74AHCT157 only: operates with TTL input levels.
  • ESD protection:.
  • HBM JESD22-A114E exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101C exc.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC157-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Nexperia

Part Number Description
74AHCT157 Quad 2-input multiplexer
74AHCT157-Q100 Quad 2-input multiplexer
74AHCT157BQ Quad 2-input multiplexer
74AHCT157D Quad 2-input multiplexer
74AHCT123A Dual retriggerable monostable multivibrator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74AHC157; 74AHCT157 Quad 2-input multiplexer Rev. 3 — 10 September 2020 Product data sheet 1. General description The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74AHC/AHCT157. The state of the common data select input (S) determines the particular register from which the data comes.