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74AHCT2G00DC - Dual 2-input NAND gate

Download the 74AHCT2G00DC datasheet PDF. This datasheet also covers the 74AHC2G00 variant, as both devices belong to the same dual 2-input nand gate family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74AHC2G00; 74AHCT2G00 are high-speed Si-gate CMOS devices.

They provide two 2-input NAND gates.

The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.

Key Features

  • Symmetrical output impedance.
  • High noise immunity.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101C exceeds 1000 V.
  • Low power dissipation.
  • Balanced propagation delays.
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC2G00DP -40 °C to +125 °C TSSOP8.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC2G00-nexperia.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74AHC2G00; 74AHCT2G00 Dual 2-input NAND gate Rev. 5 — 7 March 2019 Product data sheet 1. General description The 74AHC2G00; 74AHCT2G00 are high-speed Si-gate CMOS devices. They provide two 2-input NAND gates. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. 2. Features and benefits • Symmetrical output impedance • High noise immunity • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101C exceeds 1000 V • Low power dissipation • Balanced propagation delays • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1.