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74ALVCH162827 - 20-bit buffer/line driver

General Description

The 74ALVCH162827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity.

They have NAND output enables (nOE1 and nOE2) for maximum control flexibility.

Key Features

  • CMOS low power consumption.
  • MultiByte flow-through standard pin-out architecture.
  • Low inductance multiple VCC and GND pins for minimum noise and ground bounce.
  • Direct interface with TTL levels (2.7 V to 3.6 V).
  • Bus hold on data inputs.
  • Current drive ± 12 mA at 3.0 V.
  • Integrated 30 Ω termination resistors.
  • Complies with JEDEC standards:.
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8B/JESD36 (2.7 V to 3.6 V).
  • ES.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74ALVCH162827 20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state Rev. 2 — 19 January 2018 Product data sheet 1 General description The 74ALVCH162827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NAND output enables (nOE1 and nOE2) for maximum control flexibility. The 74ALVCH162827 is designed with 30 Ω series resisters in both the pull-up and pulldown output structures. This design reduces line noise in applications such as memory address drivers, clock drivers and bus receivers/transmitters.