74ALVCH16825DGG Datasheet PDF - nexperia 18-bit buffer/driver Specs

74ALVCH16825DGG - 18-bit buffer/driver

This page provides the datasheet information for the 74ALVCH16825DGG, a member of the 74ALVCH16825 18-bit buffer/driver family.

Datasheet Summary

Description

The 74ALVCH16825 is an 18

bit non-inverting buffer/driver with 3-state outputs for bus-oriented applications.

The 74ALVCH16825 consists of two 9-bit sections with separate output enable signals.

Features

Wide supply voltage range of 1.2V to 3.6V.
CMOS low power consumption.
MultiByte flow-through standard pin-out architecture.
Low inductance multiple VCC and GND pins for minimum noise and ground bounce.
Direct interface with TTL levels (2.7 V to 3.6 V).
Bus hold on data inputs.
Output drive capability 50 Ω transmission lines at 85 °C.
Current drive ±24 mA at 3.0 V.
Complies with JEDEC standards:.
JESD8-5.

Datasheet Details

Part number	74ALVCH16825DGG
Manufacturer	nexperia
File Size	177.81 KB
Description	18-bit buffer/driver
Datasheet	74ALVCH16825DGG Datasheet
Additional preview pages of the 74ALVCH16825DGG datasheet.

📁 Similar Datasheet

74ALVCH16825 - 18-bit buffer/driver (NXP)

74ALVCH16821 - 20-bit bus-interface D-type flip-flop (NXP)

74ALVCH16823 - 18-bit bus-interface D-type flip-flop (NXP)

74ALVCH16827 - 20-bit buffer/line driver (NXP)

74ALVCH16841 - 20-bit bus interface D-type latch (NXP)

74ALVCH16843 - 18-bit bus-interface D-type latch (NXP)

74ALVCH162240 - Low Voltage 16-Bit Inverting Buffer/Line Driver (Fairchild Semiconductor)

74ALVCH162244 - 16-bit buffer/line driver (NXP)

74ALVCH162244 - Low Voltage 16-Bit Buffer/Line Driver (Fairchild Semiconductor)

74ALVCH162244 - 3.3V CMOS 16-BIT BUFFER/DRIVER (Renesas)

Full PDF Text Transcription

Click to expand full text

74ALVCH16825 18-bit buffer/driver; 3-state Rev. 3 — 6 April 2018 Product data sheet 1 General description The 74ALVCH16825 is an 18–bit non-inverting buffer/driver with 3-state outputs for bus-oriented applications. The 74ALVCH16825 consists of two 9-bit sections with separate output enable signals. For either 9-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be LOW for corresponding nYn outputs to be active. If either output enable input is HIGH, the outputs of that 9-buffer section are in the high impedance state. The 74ALVCH16825 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

Published: Jan 4, 2021 |