74ALVCH16821 Overview
The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. Each register is fully edge triggered.
74ALVCH16821 Key Features
- Wide supply voltage range of 1.2V to 3.6V
- plies with JEDEC standard no. 8-1A
- Current drive ± 24 mA at 3.0 V
- CMOS low power consumption
- Direct interface with TTL levels
- MULTIBYTETM flow-through standard pin-out architecture
- Low inductance multiple VCC and ground pins for minimum noise
- All data inputs have bus hold
- Output drive capability 50Ω transmission lines @ 85°C
- 1D9 Data in inputs uts 2D0
