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74ALVCH32973EC - 16-bit bus transceiver and transparant D-type latch

Download the 74ALVCH32973EC datasheet PDF. This datasheet also covers the 74ALVCH32973 variant, as both devices belong to the same 16-bit bus transceiver and transparant d-type latch family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74ALVCH32973 is a 16-bit bus transceiver and transparent D-type latch with 8 independent buffers with bus hold inputs and 3-state outputs.

Key Features

  • Wide supply voltage range from 1.2 V to 3.6 V.
  • Complies with JEDEC standard JESD8-B.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • All data inputs have bus hold.
  • Output drive capability 50  transmission lines at 85 C.
  • Current drive 24 mA at VCC = 3.0 V Nexperia 74ALVCH32973 16-bit bus transceiver and transparant D-type latch; 8 buffers 3. Ordering information Table 1. Ordering information Type number Temperature range Package Name 74.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74ALVCH32973-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74ALVCH32973EC
Manufacturer Nexperia
File Size 789.87 KB
Description 16-bit bus transceiver and transparant D-type latch
Datasheet download datasheet 74ALVCH32973EC Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74ALVCH32973 16-bit bus transceiver and transparant D-type latch with 8 independent buffers Rev. 3 — 17 January 2013 Product data sheet 1. General description The 74ALVCH32973 is a 16-bit bus transceiver and transparent D-type latch with 8 independent buffers with bus hold inputs and 3-state outputs. It features direction (1DIR, 2DIR), latch enable (1LOE, 2LOE), transceiver output enable (1TOE, 2TOE) and latch enable (1LE, 2LE) control inputs; four 8-bit transceiver ports (1An, 2An & 1Bn, 2Bn); two 8-bit D-type latch output ports (1Qn, 2Qn) and an 8-bit buffer with data inputs Dn and outputs Yn.