Datasheet4U Logo Datasheet4U.com

74AUP1G34 - Low-power buffer

Description

The 74AUP1G34 is a single buffer.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Overvoltage tolerant inputs to 3.6 V.
  • Low noise overshoot and undershoot < 10 % of VCC.
  • IOFF circuitry provides partial power-down mode operation.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II.
  • Low static power consumption; ICC = 0.9 μA (maximum).
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3.

📥 Download Datasheet

Datasheet preview – 74AUP1G34

Datasheet Details

Part number 74AUP1G34
Manufacturer nexperia
File Size 273.15 KB
Description Low-power buffer
Datasheet download datasheet 74AUP1G34 Datasheet
Additional preview pages of the 74AUP1G34 datasheet.

📁 Similar Datasheet

  • 74AUP1G34 - Low-power buffer (NXP)
  • 74AUP1G34 - SINGLE BUFFER GATE (Diodes)
  • 74AUP1G32 - Low-power 2-input OR gate (NXP)
  • 74AUP1G32 - SINGLE 2 INPUT POSITIVE OR GATE (Diodes)
  • 74AUP1G3208 - Low Power 3-Input OR-AND Gate (NXP)
  • 74AUP1G332 - Low Power 3-Input OR Gate (NXP)
  • 74AUP1G373 - Low-power D-type transparent latch (NXP Semiconductors)
  • 74AUP1G386 - Low-power 3-input EXCLUSIVE-OR gate (NXP Semiconductors)
  • 74AUP1G00 - Low-power 2-input NAND gate (NXP Semiconductors)
  • 74AUP1G00 - SINGLE 2 INPUT POSITIVE NAND GATE (Diodes)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
74AUP1G34 Low-power buffer Rev. 10 — 20 January 2022 Product data sheet 1. General description The 74AUP1G34 is a single buffer. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 0.8 V to 3.6 V • CMOS low power dissipation • High noise immunity • Overvoltage tolerant inputs to 3.
Published: |