74AUP1G34 Description
The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. Pin Assignments The 74AUP1G34 is a single buffer gate with a standard push-pull output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF.
74AUP1G34 Key Features
- Advanced Ultra Low Power (AUP) CMOS
- Supply Voltage Range from 0.8V to 3.6V
- ±4mA Output Drive at 3.0V
- Low Static power consumption
- ICC < 0.9µA
- Low Dynamic Power Consumption
- CPD = 6.3pF (Typical at 3.6V)
- IOFF Supports Partial-Power-Down Mode Operation
- ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)