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74AUP1G80 - Low-power D-type flip-flop

Description

The 74AUP1G80 is a single positive-edge triggered D-type flip-flop.

Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3 V).
  • JESD8-11 (0.9 V to 1.65 V).
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8C (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114F exceeds 5000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101E exceeds 1000 V.

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Datasheet preview – 74AUP1G80

Datasheet Details

Part number 74AUP1G80
Manufacturer nexperia
File Size 290.22 KB
Description Low-power D-type flip-flop
Datasheet download datasheet 74AUP1G80 Datasheet
Additional preview pages of the 74AUP1G80 datasheet.

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Full PDF Text Transcription

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74AUP1G80 Low-power D-type flip-flop; positive-edge trigger Rev. 7 — 23 January 2023 Product data sheet 1. General description The 74AUP1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF.
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