74AUP1G80
Description
The 74AUP1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its plement will appear at the Q output.
Key Features
- Wide supply voltage range from 0.8 V to 3.6 V
- CMOS low power dissipation
- High noise immunity
- plies with JEDEC standards
- JESD8C (2.7 V to 3.6 V)
- ESD protection
- HBM JESD22-A114F exceeds 5000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
- Low static power consumption; ICC = 0.9 μA (maximum)
