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74AUP1T57 Datasheet

Manufacturer: Nexperia
74AUP1T57 datasheet preview

74AUP1T57 Details

Part number 74AUP1T57
Datasheet 74AUP1T57-nexperia.pdf
File Size 260.96 KB
Manufacturer Nexperia
Description Low-power configurable gate
74AUP1T57 page 2 74AUP1T57 page 3

74AUP1T57 Overview

The 74AUP1T57 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; All inputs can be connected directly to VCC or GND.

74AUP1T57 Key Features

  • Wide supply voltage range from 2.3 V to 3.6 V
  • High noise immunity
  • Low static power consumption; ICC = 1.5 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Overvoltage tolerant inputs to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial power-down mode operation
  • ESD protection
  • HBM JESD22-A114F Class 3A exceeds 5000 V
  • MM JESD22-A115-A exceeds 200 V

74AUP1T57 Applications

  • Wide supply voltage range from 2.3 V to 3.6 V

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