• Part: 74AUP1T57
  • Description: Low-power configurable gate
  • Manufacturer: Nexperia
  • Size: 260.96 KB
74AUP1T57 Datasheet (PDF) Download
Nexperia
74AUP1T57

Description

The 74AUP1T57 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input.

Key Features

  • Wide supply voltage range from 2.3 V to 3.6 V
  • High noise immunity
  • Low static power consumption; ICC = 1.5 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Overvoltage tolerant inputs to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial power-down mode operation
  • ESD protection
  • MM JESD22-A115-A exceeds 200 V
  • CDM JESD22-C101E exceeds 1000 V