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74AUP1T98 - Low-power configurable gate

General Description

The 74AUP1T98 is a configurable multiple function gate with level translating, Schmitt-trigger inputs.

The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input.

All inputs can be connected directly to VCC or GND.

Key Features

  • Wide supply voltage range from 2.3 V to 3.6 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Complies with JEDEC standards.
  • JESD8-12 (0.8 V to 1.3 V).
  • JESD8-11 (0.9 V to 1.65 V).
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8C (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114F Class 3A exceeds 5000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101E exceeds 1000.

📥 Download Datasheet

Datasheet Details

Part number 74AUP1T98
Manufacturer Nexperia
File Size 258.38 KB
Description Low-power configurable gate
Datasheet download datasheet 74AUP1T98 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74AUP1T98 Low-power configurable gate with voltage-level translator Rev. 7 — 27 January 2022 Product data sheet 1. General description The 74AUP1T98 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels in 3.3 V applications. This device ensures very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using IOFF.