74AUP2G80
Description
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse.
Key Features
- Wide supply voltage range from 0.8 V to 3.6 V
- High noise immunity
- complies with JEDEC standards
- JESD8-B (2.7 V to 3.6 V)
- ESD protection
- MM JESD22-A115-A exceeds 200 V
- Low static power consumption; ICC = 0.9 μA (maximum)
- Latch-up performance exceeds 100 mA per JESD78 Class II
- Inputs accept voltages up to 3.6 V
- Low noise overshoot and undershoot < 10 % of VCC
