74HC161 Datasheet PDF - nexperia Presettable synchronous 4-bit binary counter Specs

74HC161 - Presettable synchronous 4-bit binary counter

Datasheet Summary

Description

The 74HC161 is a synchronous presettable binary counter with an internal look-head carry.

Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP).

The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW.

Features

Wide supply voltage range from 2.0 V to 6.0 V.
CMOS low power dissipation.
High noise immunity.
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
Complies with JEDEC standards:.
JESD8C (2.7 V to 3.6 V).
JESD7A (2.0 V to 6.0 V).
CMOS input levels.
Synchronous counting and loading.
2 count enable inputs for n-bit cascading.
Asynchronous reset.
Positive-edge triggered clock.

Datasheet Details

Part number	74HC161
Manufacturer	nexperia
File Size	274.99 KB
Description	Presettable synchronous 4-bit binary counter
Datasheet	74HC161 Datasheet
Additional preview pages of the 74HC161 datasheet.

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Full PDF Text Transcription

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74HC161 Presettable synchronous 4-bit binary counter; asynchronous reset Rev. 5 — 16 March 2021 Product data sheet 1. General description The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET).

Published: Jul 23, 2019 |