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74HC173D - Quad D-type flip-flop

Download the 74HC173D datasheet PDF. This datasheet also covers the 74HC173 variant, as both devices belong to the same quad d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop.

Key Features

  • Complies with JEDEC standard no. 7A.
  • Input levels:.
  • For 74HC173: CMOS level.
  • For 74HCT173: TTL level.
  • Gated input enable for hold (do nothing) mode.
  • Gated output enable control mode.
  • Edge-triggered D-type register.
  • Asynchronous master reset.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC173-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HC173D
Manufacturer Nexperia
File Size 270.44 KB
Description Quad D-type flip-flop
Datasheet download datasheet 74HC173D Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74HC173 Quad D-type flip-flop positive-edge trigger Philips
74HC173 Quad D-Type Flip-Flop Texas Instruments
74HC174 Hex D-Type Flip-Flops Texas Instruments
74HC174 Hex D-type flip-flop Philips
74HC175 Quadruple D-Type Flip-Flops Texas Instruments

Other Datasheets by Nexperia

Part Number Description
74HC173 Quad D-type flip-flop
74HC174 Hex D-type flip-flop
74HC174-Q100 Hex D-type flip-flop
74HC174D Hex D-type flip-flop
74HC175 Quad D-type flip-flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC173; 74HCT173 Quad D-type flip-flop; positive-edge trigger; 3-state Rev. 4 — 25 January 2021 Product data sheet 1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs.