74HC4024-Q100 Overview
Description
The 74HC4024-Q100 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP.
Key Features
- Automotive product qualification in accordance with AEC-Q100 (Grade
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
- Low-power dissipation
- Complies with JEDEC standard no. 7A
- CMOS input levels
