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74HC4094D - 8-stage shift-and-store bus register

This page provides the datasheet information for the 74HC4094D, a member of the 74HC4094 8-stage shift-and-store bus register family.

Datasheet Summary

Description

The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Features

  • Complies with JEDEC standard JESD7A.
  • Input levels:.
  • For 74HC4094: CMOS level.
  • For 74HCT4094: TTL level.
  • Low-power dissipation.
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
  • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V.
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3.

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Datasheet preview – 74HC4094D

Datasheet Details

Part number 74HC4094D
Manufacturer nexperia
File Size 300.62 KB
Description 8-stage shift-and-store bus register
Datasheet download datasheet 74HC4094D Datasheet
Additional preview pages of the 74HC4094D datasheet.

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Full PDF Text Transcription

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74HC4094; 74HCT4094 8-stage shift-and-store bus register Rev. 10 — 21 March 2024 Product data sheet 1. General description The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow.
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