Description
The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs.
The reset is an asynchronous active LOW input and operates independently of the clock input.
Features
- Automotive product qualification in accordance with AEC-Q100 (Grade 1).
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
- Wide supply voltage range from 2.0 V to 6.0 V.
- CMOS low power dissipation.
- High noise immunity.
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
- Complies with JEDEC standards:.
- JESD8C (2.7 V to 3.6 V).
- JESD7A (2.0 V to 6.0 V).
- Input levels:.
- For 74HC1.
74HCT107-Q100 Datasheet
