Datasheet4U Logo Datasheet4U.com

74HCT109-Q100 - Dual JK flip-flop

Download the 74HCT109-Q100 datasheet PDF. This datasheet also covers the 74HC109-Q100 variant, as both devices belong to the same dual jk flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs.

It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Input levels:.
  • For 74HC109-Q100: CMOS level.
  • For 74HCT109-Q100: TTL level.
  • J and K inputs for easy D-type flip-flop.
  • Toggle flip-flop or "do nothing" mode.
  • Specified in compliance with JEDEC standard no. 7A.
  • ESD protection:.
  • MIL-STD-883, method 3015 exceeds 2000 V.
  • HB.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC109-Q100-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74HCT109 Dual JK flip-flop Philips
74HCT10 Triple 3-input NAND gate Philips
74HCT107 Dual JK flip-flop Philips
74HCT11 Triple 3-input AND gate Philips
74HCT11 Triple 3-input AND gate NXP

Other Datasheets by Nexperia

Part Number Description
74HCT109 Dual JK flip-flop
74HCT109D Dual JK flip-flop
74HCT10 Triple 3-input NAND gate
74HCT10-Q100 Triple 3-input NAND gate
74HCT107 Dual JK flip-flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC109-Q100; 74HCT109-Q100 Dual JK flip-flop with set and reset; positive-edge-trigger Rev. 2 — 1 April 2020 Product data sheet 1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described in the mode select function table. The nJ and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.