Nexperia 74HCT112D
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs.| Part No. | 74HCT112D |
|---|---|
| Datasheet | 74HCT112D Download |
| Manufacturer |  Nexperia |
| Description | Dual JK flip-flop |
| Buy | Stock & Price |
FEATURES AND BENEFITS
● Input levels:● For 74HC112: CMOS level
● For 74HCT112: TTL level
● Asynchronous set and reset
● Specified in compliance with JEDEC standard no. 7A
● ESD protection:
● HBM JESD22-A114F exceeds 2000 V
● MM JESD22-A115-A exceeds 200 V
● Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC112D -40 °C to +125 °C 74HCT112D 74HC112PW -40 °C to +125 °C 74HCT112PW Name SO16 TSSOP16
DESCRIPTION
Version plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 Nexperia 4. Functional diagram 4 10 1SD 2SD 3 11 1J 2J J SD Q 1Q 2Q 5 9 FF 1 13 1CP 2CP CP 2 12 1K 2K K RD 1Q Q 2Q 6 7 1RD 2RD 15 14 aaa-024306 Fig. 1. Logic symbol C K J C S R 74HC112; 74HCT112 Dual JK flip-flop with set and reset; negative-edge trigger 4 S 10 S 3 1J 5 11 1J 9 1 C1 13 6 C1 7 2 1K 12 1K 15 R 14 R Fig. 2. IEC logic symbol aaa-024307 Q C C C Q C C C CP C C Fig.
