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74HCT166-Q100 - 8-bit parallel-in/serial out shift register

Download the 74HCT166-Q100 datasheet PDF. This datasheet also covers the 74HC166-Q100 variant, as both devices belong to the same 8-bit parallel-in/serial out shift register family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC166-Q100; 74HCT166-Q100 is an 8-bit serial or parallel-in/serial-out shift register.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Synchronous parallel-to-serial.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC166-Q100-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HCT166-Q100
Manufacturer Nexperia
File Size 273.00 KB
Description 8-bit parallel-in/serial out shift register
Datasheet download datasheet 74HCT166-Q100 Datasheet

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Other Datasheets by Nexperia

Part Number Description
74HCT166 8-bit parallel-in/serial out shift register
74HCT166D 8-bit parallel-in/serial out shift register
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC166-Q100; 74HCT166-Q100 8-bit parallel-in/serial out shift register Rev. 2 — 9 August 2021 Product data sheet 1. General description The 74HC166-Q100; 74HCT166-Q100 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input.