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74HCT273PW - Octal D-type flip-flop

Download the 74HCT273PW datasheet PDF. This datasheet also covers the 74HC273 variant, as both devices belong to the same octal d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop.

Key Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • Input levels:.
  • For 74HC273: CMOS level.
  • For 74HCT273: TTL level.
  • Common clock and master reset.
  • Eight positive edge-triggered D-type flip-flops.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC273-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74HCT273 Octal D-type flip-flop NXP
74HCT273-Q100 Octal D-type flip-flop NXP
74HCT27 Triple 3-input NOR gate NXP
74HCT20 Dual 4-input NAND gate Philips
74HCT21 Dual 4-input AND gate Philips

Other Datasheets by Nexperia

Part Number Description
74HCT273 Octal D-type flip-flop
74HCT273-Q100 Octal D-type flip-flop
74HCT273BQ Octal D-type flip-flop
74HCT273D Octal D-type flip-flop
74HCT273DB Octal D-type flip-flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 7 — 6 September 2021 Product data sheet 1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Wide supply voltage range from 2.0 V to 6.