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74HCT280D - 9-bit odd/even parity generator/checker

This page provides the datasheet information for the 74HCT280D, a member of the 74HC280 9-bit odd/even parity generator/checker family.

Datasheet Summary

Description

The 74HC280; 74HCT280 is a 9-bit parity generator or checker.

Both even and odd parity outputs are available.

The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH.

Features

  • Word-length easily expanded by cascading.
  • Generates either odd or even parity for nine data bits.
  • Wide supply voltage range from 2.0 to 6.0 V.
  • Input levels:.
  • For 74HC280: CMOS level.
  • For 74HCT280: TTL level.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0.

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Datasheet preview – 74HCT280D

Datasheet Details

Part number 74HCT280D
Manufacturer nexperia
File Size 240.32 KB
Description 9-bit odd/even parity generator/checker
Datasheet download datasheet 74HCT280D Datasheet
Additional preview pages of the 74HCT280D datasheet.

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Full PDF Text Transcription

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74HC280; 74HCT280 9-bit odd/even parity generator/checker Rev. 4 — 16 August 2021 Product data sheet 1. General description The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.
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